The present invention relates to input/output (I/O) circuits generally and, more particularly, to a method and/or architecture for a configurable PCI clamp or high voltage tolerant I/O circuit.
Input/output (I/O) circuits are used to communicate signals between electronic circuits. For example, input/output circuits connect internal circuitry to bond pads in integrated circuits. Some applications of integrated circuits can place a voltage (VPAD) on the bond pads that is higher than the operating voltage (VCC) of the integrated circuit (chip). When the pad voltage exceeds VCC, an I/O circuit can be required to either (i) clamp the pad to the chip power supply (see the PCI specification, revision 2.2, published Dec. 18, 1998) or (ii) be high voltage tolerant (i.e., the I/O circuit can handle a voltage on the pad that is higher than the chip supply voltage).
Referring to FIG. 1, a diagram of a circuit 10 illustrating a standard PMOS output driver is shown. The circuit 10 provides a clamp from an I/O pad to a supply voltage VCCIO when a voltage at the pad (VPAD)is greater than VCCIO. However, the circuit 10 does not provide high voltage tolerance.
Referring to FIG. 2, a diagram of a circuit 20 illustrating a high voltage tolerant I/O circuit is shown. The circuit 20 provides a high voltage tolerant circuit, but no configurable clamp. When the circuit 20 is in a tristate mode (i.e., output not enabled), the n-wells of the PMOS devices will generally be a diode drop below VCCIO or VPAD, whichever has the higher voltage.
Referring to FIG. 3, a diagram of a circuit 30 illustrating a brute force implementation of a high voltage tolerant I/O circuit with clamp capability is shown. The circuit 30 includes an output driver 32 with two PMOS devices 34 and 36 in series and a HV tolerance circuit (not shown). The HV tolerance circuit can be similar to PGATE generation and n-well bias circuits of FIG. 2. The PMOS device 34 is driven by an output buffer 38. The PMOS device 36 is driven by a clamp enable signal that is level shifted to a substrate voltage (NSUB) by a level shifter 40. The voltage NSUB is the higher of the voltage VPAD or VCCIO. The circuit 30 has disadvantages of requiring a large area to implement and producing a large speed impact.
The present invention concerns an apparatus comprising one or more input/output circuits that may be configured as (i) high voltage tolerant in response to a first state of a control input and (ii) a clamp to a supply voltage in response to a second state of the control input.
The objects, features and advantages of the present invention include providing a method and/or architecture for a configurable PCI clamp or high voltage tolerant I/O circuit that may (i) provide high voltage tolerance feature that may be configured on or off, (ii) support both I/O standards requiring a clamp to VCCIO and standards requiring high voltage tolerance, (iii) use an existing PMOS output driver and tolerance circuit to clamp a pad, (iv) be implemented without requiring significant area, (v) have little speed impact, (vi) provide an I/O circuit that supports multiple I/O standards that require high voltage tolerance, (vii) provide an I/O circuit that supports the PCI specification, rev 2.2, without the addition of an external clamping diode.